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Silicon Labs /EFR32MG21B010F768IM32 /RAC_S /AUXADCEN

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Interpret as AUXADCEN

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https://regviz.com/r/Silicon Labs/BGM210LA22JNF/RAC_NS/AUXADCEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)AUXADCENAUXADC 0 (Disabled)AUXADCENINPUTBUFFER 0 (Disabled)AUXADCENLDO 0 (Disabled)AUXADCENOUTPUTDRV 0 (Disabled)AUXADCENPMON 0 (Disabled)AUXADCENRESONDIAGA 0 (Disabled)AUXADCENTSENSE 0 (Disabled)AUXADCENTSENSECAL 0 (Not_Bypassed)AUXADCINPUTBUFFERBYPASS

AUXADCINPUTBUFFERBYPASS=Not_Bypassed, AUXADCENOUTPUTDRV=Disabled, AUXADCENTSENSECAL=Disabled, AUXADCENPMON=Disabled, AUXADCENTSENSE=Disabled, AUXADCENINPUTBUFFER=Disabled, AUXADCENLDO=Disabled, AUXADCENRESONDIAGA=Disabled, AUXADCENAUXADC=Disabled

Fields

AUXADCENAUXADC

AUXADCENAUXADC

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENINPUTBUFFER

AUXADCENINPUTBUFFER

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENLDO

AUXADCENLDO

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENOUTPUTDRV

AUXADCENOUTPUTDRV

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENPMON

AUXADCENPMON

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENRESONDIAGA

AUXADCENRESONDIAGA

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENTSENSE

AUXADCENTSENSE

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENTSENSECAL

AUXADCENTSENSECAL

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCINPUTBUFFERBYPASS

AUXADCINPUTBUFFERBYPASS

0 (Not_Bypassed): undefined

1 (Bypassed): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data